Fixes shift for ARM memory operand (capstone-engine#1162)

catenacyber · aquynh · commit dcbec535eaaf · 2018-06-06T06:09:53.000+08:00
Shift is for same operand as index register
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
@@ -2111,8 +2111,8 @@ static void printT2AddrModeSoRegOperand(MCInst *MI,
 		SStream_concat0(O, ", lsl ");
 		SStream_concat(O, "#%d", ShAmt);
 		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;
+			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
+			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt;
 		}
 	}
 

Original file line number	Diff line number	Diff line change
`@@ -2111,8 +2111,8 @@ static void printT2AddrModeSoRegOperand(MCInst *MI,`
`2111`	`2111`	`SStream_concat0(O, ", lsl ");`
`2112`	`2112`	`SStream_concat(O, "#%d", ShAmt);`
`2113`	`2113`	`if (MI->csh->detail) {`
`2114`		`- MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;`
`2115`		`- MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;`
	`2114`	`+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;`
	`2115`	`+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt;`
`2116`	`2116`	`}`
`2117`	`2117`	`}`
`2118`	`2118`