I2CTarget costs about 8k of flash size on ESP32-S2, and about 11k on
ESP32-C6.  The ESP32-C6 only has about 8k remaining, so disable I2CTarget
on that SoC until more flash can be made available.

Signed-off-by: Damien George <damien@micropython.org>

So that all six supported SoCs are built by CI.

Signed-off-by: Damien George <damien@micropython.org>

Reproducer (needs to be run as one compilation unit):

    ans = (-1) ** 2.3
    aa

Fixes issue micropython#17815.

Signed-off-by: Jeff Epler <jepler@gmail.com>

This brings in:
- lora: fix SNR value in SX126x received packets
- utop: add initial implementation for ESP32
- utop: print MicroPython memory info
- utop: print IDF heap details
- urllib.urequest: add support for headers to urequest.urlopen
- aiorepl: use blocking reads for raw REPL and raw paste
- errno: add ENOTCONN constant
- logging: allow logging.exception helper to handle tracebacks
- aioble-l2cap: raise correct error if l2cap disconnects during send
- abc: add ABC base class
- aiohttp: fix partial reads by using readexactly
- aiorepl: handle stream shutdown

Signed-off-by: Damien George <damien@micropython.org>

This setting was missed in df05cae.  It's
needed for this port to pass its `tests/ports/renesas-ra/modtime.py` test.

Signed-off-by: Damien George <damien@micropython.org>

Signed-off-by: Damien George <damien@micropython.org>

Otherwise the PLL is not enabled.  These changes are adapted from
`timer_legacy.h` in ESP-IDF.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>

Also future-proofs this code for other chips. Apart form C6 and C2, all
currently supported chips use APB clock for GPTIMER_CLK_SRC_DEFAULT.

ESP32-C2 uses 40MHz PLL but APB_CLK_FREQ was 26MHz.
ESP32-C6 uses 80MHz PLL but APB_CLK_FREQ was 40MHz.

Implementation now gets the correct frequency from ESP-IDF.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>