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difftest Public
Forked from OpenXiangShan/difftestModern co-simulation framework for RISC-V CPUs
C++ Mulan Permissive Software License, Version 2 UpdatedNov 13, 2024 -
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riscv-opcodes Public
Forked from riscv/riscv-opcodesRISC-V Opcodes
Python Other UpdatedAug 28, 2022 -
core-v-docs Public
Forked from openhwgroup/programsDocumentation for the OpenHW Group's set of CORE-V RISC-V cores
Python Other UpdatedAug 23, 2021 -
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blinky Public
Forked from fusesoc/blinkyExample LED blinking project for your FPGA dev board of choice
Verilog MIT License UpdatedJan 25, 2021 -
riscv-isa-sim Public
Forked from riscv-software-src/riscv-isa-simSpike, a RISC-V ISA Simulator
C Other UpdatedDec 28, 2020 -
riscv-pk Public
Forked from riscv-software-src/riscv-pkRISC-V Proxy Kernel
C Other UpdatedNov 1, 2020 -
bender Public
Forked from pulp-platform/benderA dependency management tool for hardware projects.
Rust Apache License 2.0 UpdatedOct 23, 2020 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedSep 11, 2020 -
misc-linters Public
Forked from lowRISC/misc-lintersSome Internal Linter Scripts
Python Apache License 2.0 UpdatedSep 10, 2020 -
edalize Public
Forked from olofk/edalizeAn abstraction library for interfacing EDA tools
Python BSD 2-Clause "Simplified" License UpdatedAug 30, 2020 -
sv-parser Public
Forked from dalance/sv-parserSystemVerilog parser library fully complient with IEEE 1800-2017
Rust Other UpdatedApr 10, 2020 -
rust-elf Public
Forked from cole14/rust-elfLibrary for parsing ELF files for Rust
Rust Other UpdatedJan 19, 2020 -
serv Public
Forked from olofk/servSERV - The SErial RISC-V CPU
Verilog ISC License UpdatedSep 26, 2019 -
moore Public
Forked from fabianschuiki/mooreHDL compiler based on LLHD
Rust Apache License 2.0 UpdatedJul 15, 2019 -
riscv-cores-list Public
Forked from riscvarchive/riscv-cores-listRISC-V Cores, SoC platforms and SoCs
UpdatedApr 25, 2019 -
antlr4 Public
Forked from antlr/antlr4ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
Java Other UpdatedMar 25, 2019 -
riscv-formal Public
Forked from SymbioticEDA/riscv-formalRISC-V Formal Verification Framework
Verilog ISC License UpdatedJan 4, 2019 -
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riscv-isa-manual Public
Forked from riscv/riscv-isa-manualRISC-V Instruction Set Manual
TeX Creative Commons Attribution 4.0 International UpdatedOct 6, 2018 -
ariane Public
Forked from openhwgroup/cva6Ariane is a 6-stage RISC-V CPU
SystemVerilog Other UpdatedSep 14, 2018 -
riscv-debug-spec Public
Forked from riscv/riscv-debug-specWorking Draft of the RISC-V Debug Specification Standard
TeX Creative Commons Attribution 4.0 International UpdatedAug 30, 2018 -
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hscodesign Public
(Efficient) FLAC and FFT implementation for Altera's Nios II softcore